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(R)
September 1998
CT t ODU emen r at E PR eplac t Cente ET ed R OL /tsc por OBS mend al Sup sil.com m c r i eco chn .inte No R our Te r www o ct RSIL onta or C 88-INTE 1-8
HFA-0003, HFA-0003L
Ultra High Speed Comparator
Features
* * * * * * * * * * Low Propagation Delay (0003/0003L) . . . . . . . . . . 2.0/2.1ns Low Latch Set Up Time . . . . . . . . . . . . . . . . . . . . . . . . 0.8ns Low Offset Voltage, Drift Coefficient . . . . . 1.0mV, 4V/oC Wide Common Mode Range . . . . . . . . . . . . . . . . +5.2/-2.8V Low Power Dissipation . . . . . . . . . . . . . . . . . . . . . . 200mW Large Differential Input Resistance . . . . . . . . . . . . . . .1M Complementary ECL Outputs; 50 Driving Capability Resistor Programmable Hysteresis with HFA-0003L Pin Compatible with MAX9690/9685 and AD96685 Available in SOIC
Description
The HFA-0003/0003L are monolithic, ultra high speed, voltage comparators. These comparators combine a low input offset voltage (1.0mV) with a low propagation delay (2.0ns) to achieve a large dynamic input range. The low offset voltage also makes these comparators ideally suited for high speed, precision analog-to-digital processing applications. The circuits have differential analog inputs, and provide complementary, ECL compatible (10K and 100K) logic outputs. The outputs are capable of supplying the current required by terminated 50 transmission lines. Both outputs are open emitter structures, requiring external pull-down resistors. The recommended circuit is 50 connected to 2.0V, but any equivalent ECL termination circuit may be used. The HFA-0003L is a latched version of the HFA-0003. The latch function allows the HFA-0003L to operate in samplehold or track-hold modes, when synchronous detection is required. The Latch Enable (LE) input can be driven by a standard ECL gate. See the Applications section for more information on this feature. The HFA-0003L also has an additional feature, user programmable hysteresis. By connecting a resistor from the HYS pin to GND the user can select up to 20mV of input hysteresis. See the Applications section for more information on this feature. The HFA-0003 is pin compatible with the MAX9690, and SP9680 while providing improved performance. The HFA0003L is pin compatible with the MAX9685, AD96685, SP9685, HCMP96850, and the VC7695 while providing improved performance.
Applications
* * * * * * * Window Detector High Speed Peak Detector High Speed Threshold Detector High Speed Data Acquisition Systems Fiber Optic Decision Circuits High Speed Phase Detector Frequency Counter
Part Number Information
PART NUMBER HFA1-0003L-5 HFA1-0003L-9 HFA2-0003L-5 HFA2-0003L-9 HFA3-0003-5 HFA3-0003-9 HFA3-0003L-5 HFA3-0003L-9 TEMPERATURE RANGE 0oC to +75oC -40oC to +85oC 0oC to +75oC -40
o oC
PACKAGE 16 Lead Ceramic Sidebraze DIP 16 Lead Ceramic Sidebraze DIP 10 Pin CAN 10 Pin CAN 8 Lead Plastic DIP 8 Lead Plastic DIP 16 Lead Plastic DIP 16 Lead Plastic DIP
to
+85oC
o
0 C to +75 C -40oC to +85oC 0oC to +75oC -40oC to +85oC
Pinouts
HFA-0003 (PDIP, CDIP, SOIC) TOP VIEW
V+ +IN -IN V1 2 3 4 + 8 GND 1 (DIGITAL) 7 GND 2 (ANALOG) 6 Q OUT 5 Q OUT
HFA-0003L (PDIP, CDIP, 150 mil SOIC) TOP VIEW
GND1 1 (DIGITAL) V+ 2 +IN -IN NC LE NC 3 4 5 6 7 + 16 GND 2 (ANALOG) 15 NC 14 NC 13 NC 12 Q OUT 11 Q OUT 10 NC 9 HYS
HFA-0003L (TO-100 CAN) TOP VIEW
GND1 (DIGITAL) 10 V+ 1 +IN -IN 2 3 LE 4 5 V+ 9 GND 2 (ANALOG) 8 Q OUT 7 Q OUT 6 HYS
V- 8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved 3-33
File Number
2749.5
DB500
Specifications HFA-0003, HFA-0003L
Absolute Maximum Ratings (Note 1)
Supply Voltage (GND to V+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V Supply Voltage (GND to V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . 20V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V Differential Ground Voltage (GND1 to GND2). . . . . . . . . . . . . . . . 1V Short Duration Output Current (Note 2) . . . . . . . . . . . . . . . . . -35mA Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Junction Temperature (Plastic Package) . . . . . . . . . . . . . . . +150oC Lead Temperature (Soldering 10 Sec.) . . . . . . . . . . . . . . . . +300oC
Operating Conditions
Operating Temperature Range HFA-0003/HFA-0003L-9 . . . . . . . . . . . . . . . . -40oC TA +85oC HFA-0003/HFA-0003L-5 . . . . . . . . . . . . . . . . . . 0oC TA +75oC Storage Temperature Range . . . . . . . . . . . . . -65oC TA +150oC Thermal Package Characteristics (oC/W) JA JC 8 Lead Ceramic Sidebrazed DIP . . . . . . . 75 13 8 Lead Plastic DIP . . . . . . . . . . . . . . . . . . 96 34 8 Lead SOIC . . . . . . . . . . . . . . . . . . . . . . 157 43 16 Lead Ceramic Sidebrazed DIP . . . . . . 75 13 16 Lead Plastic DIP . . . . . . . . . . . . . . . . . 92 32 16 Lead SOIC . . . . . . . . . . . . . . . . . . . . . 114 35 TO-100 Metal CAN . . . . . . . . . . . . . . . . . 108 32
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications V+ = 5V, V- = -5.2V, RL = 50 to -2V, Unless Otherwise Specified
HFA-0003-5/-9 PARAMETER INPUT CHARACTERISTICS Input Offset Voltage (VOS) +25oC Full Average Offset Voltage Drift (Note 8) Input Bias Current Full +25oC Full Input Offset Current +25 C Full Common Mode Range Differential Input Resistance Common Mode Input Resistance Input Capacitance TRANSFER CHARACTERISTICS Large Signal Voltage Gain +25oC Full Common Mode Rejection Ratio (Note 3) Tracking Bandwidth (Note 4) SWITCHING CHARACTERISTICS Propagation Delay Input to Output (tPD)(Notes 5, 8, 9) Maximum Dispersion (Notes 6, 8) OUTPUT CHARACTERISTICS Output Voltage Level: Logic Low (VOL) +25oC Full Logic High (VOH) +25oC Full -0.938 -1.05 -1.83 -1.83 -0.85 -0.96 -1.65 -1.57 -0.938 -1.05 -1.83 -1.83 -0.85 -0.96 -1.65 -1.57 V V V V +25oC Full Full 2.0 2.4 2.8 200 2.1 2.6 3.0 200 ns ns ps +25 C Full +25oC
o o
HFA-0003L-5/-9 MAX MIN TYP MAX UNITS
TEMPERATURE
MIN
TYP
-2.8 -
1 5 8 0.15 1 9.5 1
3 4 4 8 13 0.2 0.3 +5.2 -
-2.8 -
1 5 8 0.15 1 9.5 1
3 4 4 8 13 0.2 0.3 +5.2 -
mV mV V/oC A A A A V M M pF
Full +25 C +25oC +25oC
o
70 70 -
3100 1200 75 270
-
70 70 -
3100 1200 75 270
-
V/V V/V dB dB MHz
3-34
Specifications HFA-0003, HFA-0003L
Electrical Specifications V+ = 5V, V- = -5.2V, RL = 50 to -2V, Unless Otherwise Specified (Continued)
HFA-0003-5/-9 PARAMETER Continuous Output Current (Note 2) LATCH CHARACTERISTICS (HFA-0003L ONLY) LE Input Voltage Level: Logic Low (VIL) Logic High (VIH) LE Input Current Level: Logic Low (VIL = -1.85V) Logic High (VIH = -0.81V) Propagation Delay from LE to Output (tPDL) (Notes 5, 8, 9)
HFA-0003L-5/-9 MAX -30 MIN TYP MAX -30 UNITS mA
TEMPERATURE Full
MIN -
TYP -
Full Full
-
-
-
-1.105
-
-1.475 -
V V
Full Full +25
oC
-
-
-
-
0.06 11 2.2 2.6 0.8 0.5 0.9 -
0.5 20 2.7 3.1 1.2 1.5 1.0 0.95 1.1
A A ns ns ns ns ns ns ns
Full +25 C Full
o
Minimum Set-Up Time (tS) (Notes 8, 9)
Minimum Hold Time (tH) (Notes 8, 9) Minimum LE Pulse Width (tPW) (Notes 8, 9) POWER SUPPLY PSRR (Note 7)
Full +25 C Full
o
+25oC Full
70 65 -
80 11 19 -
13 22 200
70 65 -
80 11 19 -
13 22 200
dB dB mA mA mW
ICC IEE Power Dissipation NOTES:
Full Full Full
1. Absolute maximum ratings are limiting values, applied individually, beyond which the servicability of the circuit may be impaired. Functional operation under any of these conditions is not necessarily implied. Exposure to absolute maximum rating conditions may affect device reliability. 2. Outputs have no sink current (+I) capability, since they are open emitter NPN transistors. 3. -2.0V VCM +4.0V. 4. Tracking Bandwidth (TBW) is defined as the maximum input frequency at which the outputs still switch between V OL and VOH. VIN = 15mVp-p sinewave centered on 0V. 5. V IN = 100mV. VOD is the amount of input overdrive. 6. Dispersion is defined as the change in propagation delay for input overdrives between 0.1V and 1.0V. 7. +4.5V V+ +5.5V or -6.2V V- -4.7V. 8. This parameter is not tested. It is guaranteed by design, and by device characterization. 9. VOD = 10mV.
3-35
HFA-0003, HFA-0003L Applications Information
HFA-0003L Latch Functionality The Latch Enable (LE) pin of the HFA-0003L controls the function of the on chip latch. When the LE input is at an ECL Logic 1, the latch is open (transparent) and the comparator functions normally. When the LE input switches to a Logic 0, the outputs are latched in unambiguous states dependant on the current input state, providing the set-up and hold times are met. If the latch function is not utilized, the LE input must be connected to an ECL Logic 1 (e.g. GND). HFA-0003L Hysteresis Functionality To improve performance in systems with slow transition times, and/or high noise levels, the HFA-0003L allows the user to easily set the amount of input hysteresis. The hysteresis level is set by the current flowing into the HYS input; the larger the current the larger the level of hysteresis. This current is provided by connecting a resistor (R H) between the HYS pin and GND, and it is recommended that the input current not exceed 1mA. The input current can be approximated from the following formula:
Timing Diagram GND - ( V- ) - 0.7V
COMPARE
IH = ------------------------------------------------R H
LATCHED 50% tPW
The table below gives approximate levels of hysteresis for some values of IH, at TA = +25oC.
LE
IH (mA)
IN
0.2
VIN
tS
0.4
VOD
0.6 8
tH
0.8 13
1.0 22
HYS (mV)
1
4
VOS tPDL
If the hysteresis function isn't used, the HYS input may be tPD left floating, or may be connected to V-. The HYS input Q MUST NEVER BE CONNECTED directly to GND or V+, as device damage will occur. Before inserting an HFA-0003L into a competitor socket, the user must ensure that the corresponding socket pin is a true no connect (i.e. is floating).
Q
50%
50%
3-36

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